[Linux-ivv4] Fwd: Intel Software: Spring/Summer Webinar Series. Register now!
Adam, Heinz-Hermann
adamh at uni-muenster.de
Di Mai 20 11:44:20 CEST 2014
Begin forwarded message:
> From: "Jaworska, Joanna" <joanna.jaworska at intel.com>
> Subject: Intel Software: Spring/Summer Webinar Series. Register now!
> Date: 20. Mai 2014 10:01:41 MESZ
> Cc: "Preiss, Edmund" <edmund.preiss at intel.com>, "Jaworska, Joanna" <joanna.jaworska at intel.com>
>
> Dear customer,
>
> We would like to invite you to the latest Intel® Software Development Tools Webinar Series which will cover a wide range of new Intel tools aspects and development aspects.
>
> This webinar is closely related to the ongoing Intel beta program for the new Intel Parallel Studio XE 2015 bundle with target launch date in Q3 2014.
>
> Scope:
>
> These free technical webinars cover tips and techniques that will help sharpen your development skills to create faster, more reliable applications.
> Technical experts will cover topics ranging from vectorization, code migration, code optimization, using advanced threading techniques (e.g., OpenMP 4.0, Intel® Cilk™ Plus, Intel® TBB), and error checking.
>
> Feel free to bring programming questions to the live session for our technical experts to answer.
>
> A replay of each webinar will be available shortly after the live session so you can share with those unable to attend the live session.
>
> Webinar Series
> Time zone is U.S Pacific time but the sessions will be recorded and will be available for on-demand access later.
> The URL to go to for further information and to register is :
> https://software.intel.com/en-us/articles/intel-software-tools-technical-webinar-series
>
> Please take a look at the agenda below:
>
> Date and Time
>
> Topic
>
> Webinar Details
>
> Presenter
>
> Registration
>
> May 6
> 9:00 A.M.
> Pacific
>
> Flow Graph with Intel® Threading Building Blocks
>
> The hardware landscape has changed from being mostly serial to mostly parallel in the past 5-10 years. A lot of effort has gone into enabling software to take advantage of the increase in computing power in modern parallel machines, but most software available today offer limited scalability. Developers have spent a lot of time adding incremental parallelism, mostly addressing the data parallel code regions, but the rest of application remains serial. A robust design of a concurrent system is applicable to many areas of engineering from embedded systems to scientific computing. Designing such systems using dataflow-oriented models can expose large amounts of concurrency to system implementation that otherwise go unharnessed. Utilizing this concurrency effectively enables distributed or parallel execution and increased throughput, or reduced power usage at the same throughput. This lecture discusses the importance of building such robust systems by mapping the actor/agent paradigm to your algorithm or code and implementing the system using the new flow graph feature introduced in Intel® Threading Building Blocks (Intel® TBB) 4.0. TBB flow graph feature allows users to easily create flow graphs and dependency graphs that execute on top of Intel TBB tasks. Users programmatically create nodes and edges that express the computations performed by their application and the dependencies between these computations. The Intel TBB library is then able to exploit the parallelism that is implicit in the graph structure, and the resources available on the target machine, to speed up the application. Flow graphs are applicable across a wide range of domains, including media, gaming, finance, portable/low-power computing, big data analytics and technical computing. An overview of the Actor/Agent paradigm will be presented and the audience will be walked through the details of simple and complex examples that demonstrate the power and flexibility of this parallel programming abstraction. The challenges of debugging and performance tuning of such constructs will be outlined and explored through traditional profiling techniques and a prototype tool chain.
>
> Kevin O'Leary
>
> REGISTER
>
> May 13
> 9:00 A.M.
> Pacific
>
> Find Bugs Quickly and Easily in Your Fortran Application Using Intel® Inspector XE
>
> This webinar will present the debugging and analysis capabilities of Intel® Inspector XE with a focus on Fortran development. Quickly detect and locate threading and memory issues in your application, and correlate those issues to the exact line of source code causing the problem. The presentation will include specific examples of common errors and how Intel® Inspector XE can greatly aid in the debugging process.
>
> Jackson Marusarz
>
> REGISTER
>
> May 20
> 9:00 A.M.
> Pacific
>
> Tachyon ray tracer port on Intel® Xeon Phi™ coprocessor
>
> This webinar will present a practical case study of porting the Tachyon, an open source ray tracer, part of the SpecMPI suite, to Intel® Xeon Phi™ coprocessor. The Initial port revealed disappointing performance, e.g. the combined Intel® Xeon® processor and Intel Xeon Phi coprocessor version ran 2.6x slower than Xeon-only version. To achieve good performance some code modifications needed to be introduced improving both processor and coprocessor parts. Intel® Cluster Studio XE is used to pinpoint the problems and will highlight key code changes which helped achieve significant improvements (up to 7x vs from initial baseline, and 1.8x speed up vs improved Xeon version). The application exploits parallelism at multiple levels - symmetric MPI execution model, OpenMP-based multi-threading, and explicit SIMD (using SSE2/AVX/Xeon Phi instructions). Several software tools will be highlighted – Intel® Trace Analyzer and Collector, and Intel® VTune™ Amplifier XE in combination with MPI* and OpenMP* programming models, as well as a SIMD-enabled 3D vector operations library (reused and extended from Embree, the open source ray tracer by Intel Labs). Algorithmic changes include MPI-based dynamic scheduling, introduction of explicit intrinsics-based SIMD support, enabling greater OpenMP parallelism capacity.
>
> Roman Lygin
>
> REGISTER
>
> May 27
> 9:00 A.M.
> Pacific
>
> An Introduction to Intel® Visual Fortran Development on Intel® Xeon Phi™ coprocessor
>
> The Intel® Visual Fortran Composer XE SP1 release includes support for Intel® Xeon Phi™ coprocessors on Windows*. This webinar introduces the development environment for developing Fortran applications for the Intel® Xeon Phi™ coprocessor for Windows*. You will learn about the system configuration including details of the Intel® Manycore Platform Software Stack (Intel® MPSS), integrations with Microsoft Visual Studio*, Fortran offload programming models, developing and debugging offload and native applications, and existing limitations.
>
> Kevin Davis
>
> REGISTER
>
> Jun 3
> 9:00 A.M.
> Pacific
>
> Intel® VTune™ Amplifier XE Overview and New Features
>
> This webinar will give an overview of the VTune™ Amplifier XE features including: first use tips, performance collection modes (Hotspots, General Exploration, Locks-And-Waits), and tuning occasional random slowdowns. In addition, some of the VTune™ Amplifier XE's newer features will be discussed: launching a data collection remotely, Intel® Xeon Phi™ coprocessor support, tips on speeding up the analysis phase, OpenMP support, some cluster support, and Pause/Resume APIs. We will also discuss some upcoming features such as running the VTune™ Amplifier XE analysis GUI on a Mac.
>
> Gary Carleton
>
> REGISTER
>
> Jun 10
> 9:00 A.M.
> Pacific
>
> Intel MPI library implementation of a new MPI3.0 standard - new features and performance benchmarks.
>
> Introduction into implementation of a new MPI-3 standard by the latest Intel MPI library 5.0. MPI 3.0 standard introduced many new features such as new one-sided (Remote Memory Access (RMA)) communication semantics, non-blocking and neighborhood collectives, improvements in Fortran bindings and fault tolerance. New MPI 3.0 standard targets to improve performance, reliability and ease of use of HPC cluster applications. In this webinar we will cover MPI 3.0 features implemented in Intel MPI 5.0 library (beta) illustrated by small examples codes. Complementing release of Intel MPI 5.0, we also release a new version of Intel micro-benchmarks library IMB 4.0 containing the benchmarks for non-blocking collectives and new RMA interface. To observe performance benefits with these benchmarks, the asynchronous progress support in multi-threaded version of Intel MPI 5.0 library was implemented . The preliminary performance results based on IMB 4.0 show 2x performance advantage of non-blocking collectives for medium and large message sizes. We will also demonstrate performance advantages of truly passive RMA put function invocation in IMB 4.0 test-suite. Finally, a small stencil kernel will be used to demo a new shared memory MPI API functions that can compete with hybrid MPI and OpenMP applications.
>
> Mark Lubin
>
> REGISTER
>
> Jun 17
> 9:00 A.M.
> Pacific
>
> Sparse Linear Algebra Functions in Intel® Math Kernel Library
>
> Sparse matrix algorithms are encountered in a broad range of important scientific computing applications. Intel MKL offers a powerful set of functions that can be used to build a complete solution to many sparse linear systems. This webinar gives an overview on MKL's sparse linear algebra component. Highlights include Sparse BLAS functions, Direct solvers for sparse linear systems, Iterative solvers and Eigensolvers for sparse matrices based on the FEAST algorithm.
>
> Zhang Zhang
>
> REGISTER
>
> Jun 24
> 9:00 A.M.
> Pacific
>
> Remodel your Code with Intel® Advisor XE
>
> Thanks to the multi-core era, it has become imperative for software developers to exploit parallelism inherent in their applications. Intel® Advisor XE helps make incorporating threading into applications easier by allowing developers to model parallelism. It inculcates in software developers a disciplined approach to exploiting parallelism. Inte® Advisor XE obviates guesswork and trial-and-error based approaches, and instead guides developers to confidently model and transform serial portions of code to parallelized versions in a step by step methodical fashion.
>
> The presenter will introduce the Intel® Advisor XE tool and demonstrate a structured approach to exploiting parallelism that Intel® Advisor XE facilitates. Attendees of this webinar will gain:
>
> · Understanding of the importance of approaching parallelization problems based on measured data rather than guesswork
> · The importance of performing parallelism modeling using Intel® Advisor XE annotations and analyses so that correct portions of your software can be judiciously selected and parallelized
> · Knowledge of resources, including a clear step-by-step process, for implementing threading in software
> Ravi Vemuri
>
> REGISTER
>
>
> You can also access all the archived webinars here.
>
> Please also note that you can unsubscribe from further notifications of this type.
>
> In case please respond to this email with “Unsubscribe” message on top of the message or in the subject line.
>
> Best Regards,
> Joanna Jaworska and Edmund Preiss
>
>
> Intel Corporation
> Phone: +49 8999143233
> Mobile: +49 17672584748
> e-mail: joanna.jaworska at intel.com
> http://www.intel.com/software/products
>
>
>
> Intel GmbH
> Dornacher Strasse 1
> 85622 Feldkirchen/Muenchen, Deutschland
> Sitz der Gesellschaft: Feldkirchen bei Muenchen
> Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk
> Registergericht: Muenchen HRB 47456
> Ust.-IdNr./VAT Registration No.: DE129385895
> Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052
>
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